Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
ICs use various sorts of devices to create logic circuits. Many types of ICs use complementary metal-oxide-semiconductor (“CMOS”) logic circuits. CMOS logic circuits use CMOS cells that have a first-conductivity-type metal-oxide-semiconductor (“MOS”) field-effect transistor (“FET”) (e.g. a P-type MOS (“PMOS”) FET) paired with a second-conductivity-type MOS transistor (e.g. an N-type MOS (“NMOS”)FET). CMOS cells can hold a logic state while drawing only very small amounts of current.
It is generally desirable that MOS transistors, whether used in a CMOS cell or used individually, provide good coupling between the gate electrode and the channel when operating voltage is applied to the gate of the MOS transistor. A conductive, uniform gate electrode promotes FET operation.
Amorphous silicon, poly-silicon, metal, and silicides have all been used as gate electrode materials. Silicide gates are desirable because they provide high conductivity and allow subsequent high-temperature processing. Typically, poly-silicon or amorphous silicon is deposed onto the wafer and nickel, cobalt, titanium, or other suitable metal is deposited over the silicon using well-known deposition and patterning techniques. The wafer is heated so that the metal layer combines with the silicon to form a silicide gate electrode. A fully silicided gate electrode is commonly referred to as a “FUSI” gate.
However, the silicon layer that is used to form the silicide gate electrode is relatively thick, and sometimes the composition of the gate electrode material at the interface with the gate dielectric layer is not uniform. If full silicidation is not achieved at the gate dielectric-gate electrode interface, the threshold voltage of the device may be adversely affected.
If silicidation, which occurs from the metal-silicon interface toward the gate electrode-gate dielectric interface, is not complete, the gate electrode-gate dielectric interface can be rough, and the silicide, whether completely or partially reacted, can penetrate into the gate dielectric, which also affects FET performance because it provides areas under the gate electrode that are closer to the channel than other areas, resulting in inconsistent threshold voltage and higher leakage current. Ultimately it may even damage the gate oxide and cause a functional failure of the device.
It is desirable to provide a FET device having an improved gate electrode structure and improved operation.